EDN

Cadence promises full SystemVerilog support

SAN JOSE, Calif. — As 26 EDA vendors presented their plans for SystemVerilog support at the Design Automation Conference last week, Cadence Design Systems was notably missing. But Cadence, which ...
EDN

SystemVerilog adoption up, Cadence survey says

SANTA CRUZ, Calif. — A recent user survey shows that adoption of the SystemVerilog language is growing rapidly, according to Cadence Design Systems. Further, the survey found, over half of ...
Design-Reuse

Cadence OVM SystemVerilog Solution Enables More Thorough Verification and Reduces Costs at Mitsubishi Electric

SAN JOSE, Calif., 25 Jan 2010-- Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, announced today that Mitsubishi Electric Corp. has adopted Cadence® ...
Business Wire

Cadence and Mentor Graphics Deliver Interoperability with Open SystemVerilog Verification Methodology

SAN JOSE, Calif., & WILSONVILLE, Ore.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (NASDAQ:CDNS), and Mentor Graphics Corp. (NASDAQ:MENT) today announced that they will standardize on a verification ...
Design-Reuse

Cadence Extends the Open Verification Methodology Beyond SystemVerilog to Include SystemC and e Language Support

SAN JOSE, Calif. -- Feb 23, 2009 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, today announced the release of open source libraries for e and ...
Electronic Design

Cadence, Mentor Team To Open Up SystemVerilog Verification

When the SystemVerilog hardware description language (HDL) came onto the scene a few years ago, it promised true openness and interoperability. Here, crowed the hype, was an HDL that would enable ...
Electronic Design

Cadence And Mentor Develop Open-Source SystemVerilog Methodology

EDA giants Cadence Design Systems and Mentor Graphics announced that they will create and standardize on a verification methodology based on the IEEE 1800(TM)-2005 SystemVerilog standard. Using the ...